Specifications

Oct. 3, 2022  ONFI 5.2 Spec

Published in Oct of 2024, ONFI5.2 adds the Separate Command Address (SCA) Protocol and other errata related to the ONFI5.1 specification

May 14, 2024  ONFI 5.1 Errata

August 11, 2022  ONFI 5.1 Spec

Published in Aug of 2022, ONFI5.1 extends NV-DDR3 and NV-LPDDR4 I/O speeds up to 3600MT/s. To support the faster data rates, ONFI5.1 introduces Write Duty Cycle Adjustment (WDCA), Per-Pin VrefQ Adjustment, Equalization and Unmatched DQS options for NAND vendors. ONFI5.1 also adds ESD specifications, makes adjustments to tDQSRE and tDQSRH specifications and relaxes data input/output pre-amble timings for NV-DDR2/3 to tWPRE2/tRPRE2. ONFI5.1 also includes other errata related to the ONFI5.0 specification.

December 6, 2023  ONFI 5.0 Errata

May 25, 2021  ONFI 5.0 Spec

Published in May of 2021, ONFI5.0 extends NV-DDR3 I/O speeds up to 2400MT/s. A new NV-LPDDR4 lower power interface is introduced with speeds up to 2400MT/s. With the NV-LPDDR4 interface, an optional Data Bus Inversion (DBI) feature is defined. New smaller footprint BGA-178b, BGA-154b and BGA-146b packages are added. ONFI5.0 also includes other errata related to the ONFI4.2 specification.

January 28, 2022  ONFI 4.2 Errata

Feb. 12, 2020  ONFI 4.2 Spec

Published in February of 2020, ONFI 4.2 extends NV-DDR3 I/O speeds to 1333MT/s, 1466MT/s and 1600MT/s. The BGA-252b four channel package is introduced which has a smaller footprint than the existing BGA-272b four channel package. To enable higher IOPS multi-plane operations, addressing restrictions related to multi-plane operations are relaxed. ONFI4.2 also includes other errata related to the ONFI4.1 specification.

Oct. 21, 2019  JEDEC Standard JESD230D

This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup (ONFI).

Jan. 7, 2020  ONFI 4.1 Errata

Dec. 12, 2017  ONFI 4.1 Spec

Published in December of 2017, ONFI 4.1 extends NV-DDR3 I/O speeds to 1066 MT/s and 1200MT/s. For better signaling performance, ONFI 4.1 adds Duty Cycle Correction (DCC), Read and Write Training for speeds greater than 800MT/s, support for lower pin cap devices with 37.5 Ohms default output resistance, and devices which require data burst exit and restart for long data input and output pauses. For lower power, 2.5V Vcc support is added. ONFI 4.1 also includes errata to the ONFI 4.0 specification.

Nov. 2016  JEDEC Standard JESD230C

JEDEC announced the release of JESD230C, NAND FLASH INTERFACE INTEROPERABILITY, published November 2016. This document is now available free of charge on the JEDEC website at: http://www.jedec.org/standards-documents/results/jesd230

This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup (ONFI).

Jan. 24, 2018  ONFI 4.0 Errata

Apr. 2, 2014  ONFI 4.0 Spec

Published in April of 2014, ONFI 4.0, introduces the evolutionary NV-DDR3 interface with VccQ = 1.2V operation for increased performance and improved power consumption, scales NV-DDR2 and NV-DDR3 I/O speed to 667 MT/s and 800 MT/s, and adds ZQ calibration functionality. ONFI 4.0 also adds electrical package specifications and includes errata to the ONFI 3.2 specification.

July 3, 2014  JEDEC Standard JESD230B

JEDEC announced the release of JESD230B, NAND FLASH INTERFACE INTEROPERABILITY, published July 2014. This document is now available free of charge on the JEDEC website at: http://www.jedec.org/standards-documents/results/jesd230

This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup (ONFI).

Aug. 12, 2013  ONFI 3.2 Errata

June 13, 2013    ONFI 3.2 Spec

Published in June of 2013, ONFI 3.2 includes errata to the ONFI 3.1 specification, scales NV-DDR2 I/O speed to 533 MT/s, and introduces four channel packages (BGA-316 and BGA-272) to enable small form factor SSDs.

Nov. 1, 2012    JEDEC Standard JESD230

JEDEC announced the release of JESD230, NAND FLASH INTERFACE INTEROPERABILITY, published October 2012. This document is now available free of charge on the JEDEC website at: http://www.jedec.org/sites/default/files/docs/JESD230.pdf

This document defines a standard NAND flash device interface interoperability standard that provides means for a system to be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup (ONFI).

Oct. 12, 2012  ONFI 3.1 Errata

Sep. 21, 2012    ONFI 3.1 Spec

Published in October of 2012, ONFI 3.1 includes errata to the original ONFI 3.0 specification, adds LUN SET/GET Features commands, and implements additional data setup and hold values for NV-DDR2 interface.

Sep. 20, 2012  ONFI 3.0 Errata

Mar. 15, 2011    ONFI 3.0 Spec

Announced in March of 2011, ONFI 3.0 extends the benefits of the ONFI spec:

• promotes a high-speed NAND Flash interface supporting transfer rates up to 400 MB/s
• requires fewer chip enable pins enabling more efficient PCB routing
• designed for the future and supports the EZ-NAND interface

Oct. 19, 2011    ONFI 2.3a Spec

Published in October 2011, ONFI 2.3 includes errata to version 2.2 and adds details on the EZ-NAND (ECC ZERO NAND) interface.

June 7, 2010 ONFI 2.2 Errata

Oct. 7, 2009    ONFI 2.2 Spec

Ratified in October of 2009, ONFI 2.2 provides several useful new features:

• Individual LUN reset
• Enhanced program page register clear
• New Icc specs and measurement

LUN reset and page register clear enable more efficient operation in larger systems with many NAND devices, while the standardized Icc testing and definitions will provide simplified vendor testing and improved data consistency.

Oct. 20, 2009  ONFI 2.1 Errata

Jan. 14, 2009    ONFI 2.1 Spec

ONFi 2.1 was ratified in January of 2009 and contains a plethora of new features that deliver speeds of 166 MB/s and 200 MB/s, plus other enhancements to increase power, performance, and ECC capabilities.

Feb. 10, 2009 ONFI 2.0 Errata

Dec. 28, 2006    ONFI 1.0 Spec

ONFI 2.0 defines a high-speed NAND Flash interface that can deliver speeds greater than 133 MB/s, whereas the legacy NAND interface was limited to 50 MB/s. The full ONFI 2.0 specification was released in February of 2008.

Nov. 28, 2007  ONFI 1.0 Errata

Dec. 28, 2006    ONFI 1.0 Spec

The ONFI 1.0 specification was developed to enable NAND Flash devices to self-describe their capabilities to host systems. This facilitates:

• Faster integration into host platforms
• The ability to add a new NAND device to an existing solution without firmware or software modifications

The specification also standardizes the NAND command set and establishes infrastructure for future evolution of NAND Flash capabilities, providing flexibility for supplier-specific optimizations.

Apr. 23, 2008  NAND Connector 1.0 Spec

The NAND Connector Specification was ratified in April of 2008. It specifies a standardized connection for NAND modules (similar to DRAM DIMMs) for use in applications like caching and SSDs in PC platforms.

Feb. 27, 2008  Block Abstracted NAND Errata

July 8, 2009    Block Abstracted NAND Spec 1.1

ONFI created the Block Abstracted NAND addendum specification to simplify host controller design by relieving the host of the complexities of ECC, bad block management, and other low-level NAND management tasks. The ONFI Block Abstracted NAND revision 1.1 specification adds the high speed source synchronous interface, which provides up to a 5X improvement in bandwidth compared with the traditional asynchronous NAND interface.

The ONFI Workgroup continues to evolve the ONFI specifications to meet the needs of a rapidly growing and changing industry.